Micro Processor BCA-3
Micro Processor BCA-3
1. Two's complement representation of -2 is__
a) 110 b)0110 c)1110 d)none of these
2. the binary representation of decimal number 0.375 is___
a) 1110 b)01110 c)0.011 d)1.001
3.8085 model includes ___-register
a) one b)two c)six d)seven
4.8085 has ____ general purpose register to store ___ bit data
a) one ,3 b)two ,4 c) six,8 d)none of these
5. this 16 bit register deals with sequencing the execution of instructions_
a)ac b)dc c)pc d)none of these
6. the beginning of the stack is defined by loading 16 bit address in the ____
a)pc b)ac c)sp d)none of these
7.the size of 8085 address bus is ____ bit
a) two b)three c )16 d)8
8.state TRUE/False ; trap is an un makeable interrupt.
a) FALSE b) TRUE c)NO comment d)Both a & b
9. these two pins provide connection for an external frequency_____
a)A,B b) A,C c)x1,x2 d)none of these
10_________ flag is set to 1 by the instruction just ending if the A register contains a result of all 0's
a)Non Zero b)Carry c)Zero d)None of thes
11 Ac flag is set to a 1 by the instruction just ending if a carry occurred from bit _ to bit___ of the A register during the instruction's execution
a) 1,2 b) 2,3 c)3,4 d)2,3
12.in the case of ____ addressing mode , the instruction directly specifies the absolute location of the data
a)indirect b) xdirect c)direct d)none of these
13.in a three byte instruction , the first byte specifies the opcode , and the following two bytes specify the______
a) 8-bit b) 2 bit c)16 bit d)none of these
14.the LDA instruction moves a byte from memory in to _____ register
a) B register b) c register c)A register d)none of these
15. the CMC and STC instruction allow direct control of the ____ flag by the programmer.
a) Zero flag b) AC flag c) carry flag d)none of these
16. when the OPUSH PSW is encountered the contents of the _ is pushed onto the stack first ,followed by the ____
a)A register ,Byte b) A register, B flag c)A register, flag byte d)none of these
17. the function of the program counter is to point to the memory address from which ____ is to be fetched.
a)first byte b) prv. byte c)next byte d)none of these
18. The___ instruction causes the contents of H&L register to be exchanged with the two bytes which are currently on the top of the system stack.
a)XTPL b)XTML c)XTHL d)HTML
19. ___ flag of the 8086 is set if there is a carry out of bit 3 during an addition operation
a) carry flag b)Zero flag c) Auxiliary carry flag d)none of these
20. ____ register is used an implied counter by creation instructions
a)AX b) Bx c) Cx d)none of these
21state TRUE?FALSE if the DF is cleared ,the string is processed from the higher address towards the lower address
a)TRUE b) FALSE c)no comment d)None of these
22. the size of effective address of 8086 is ___ bits
a) 8 b)12 c)16 d) 32
23.State TRUE/FALSE instruction register of 8086 is LIFO queue
a)TRUE b) FALSE c)no comment d)None of these
24. the next instruction being executed is pointed by_ register
a) Ac b) BC c)PC d)none of these
25.the addressing mode in which the effective address of the datum is in the BX or an index register is_____
a)direct b)register direct c)indirect d)none of these
26. state TRUE?FALSE if a displacement or immediate operand is 2 bytes long, the lower order byte always first
a)TRUE b) FALSE c)no comment d)None of these
27. which field of an instruction indicates what the computer is to do
a) operand b) instruction c) opcode d)none of these
28. the execution time of an instruction can be determined by multiplying the number of clock cycles needed to execute the instruction by the _____
a) cycle b)alarm c)Clock period d)None of these
29. state TRUE/FALSE for a given two operand instruction a register to memory operation is slower than a memory to register operation.
a)TRUE b) FALSE c)no comment d)None of these
30.___ the size of 8086 instruction
a) 1 byte b) 2 bye c) 1 to 6 byte d) 1to 32 byte
31 A _ is an identifier that is assigned the address of the first byte of the instruction in which it appears
a)label b)statement c) goto d)none of these
32. if there are two operands the ____ operand appears first
a) source b)destination c)Both d)none of these
33.state TRUE/FALSE LEA instruction does not affect flags.
a)TRUE b) FALSE c)no comment d)None of these
34.state TRUE/FALSE Neither operand in the XCHG instruction can be immediate
a)TRUE b) FALSE c)no comment d)None of these
35.the CBW and CWD instruction, are designed to aid the ______ process.
a) plus b) minus c) sign extension d)none of these
36. The INC,DEC and NEG instruction have ___ operands
a) one b)Two c)three d)Four
37. The ____ flag is needed to indicate the carry out of bit 3,the MSB of the low order nibble
a)CF b)DF c)AF d)DF
38.in conditional branch instructions ,the distance between the address of the next instruction and branch address to the range _____ byte
a)0 to 127 b) 125 to 255 c) 128 to 127 d)None of these
39. All conditional branch instruction have the ____ byte machine code format.
a) one b)Two c)three d)Four
40.A___ instruction causes the computer to cease its operations.
a) DLT b)CLT c)HLT d)ADS
41.The instruction used to clear interrupt flag in 8086 is_______
a)CLI b) HLT c)CWX d)None of these
42. ______ instruction does not automatically insert zeroes from the left, instead extends the sign of the operand by repeatedly inserting the MSb
a)SAR b)BAR c)CAR d)DAR
43. The instruction used to rotate left through carry is________
a)ACL b)BCL c)RCL d)None of these
44.the directive used to define a Double Word is______
a)DD b)BB c)CC d)None of these
45. The directives and instruction that appear between the _______ directives are considered to be contained in the segment.
a) segment b)Record c)ENDS d)Both a and c
46,. The output of an assembler is______-
a) Object Module b)Listing c)Both a and b) d)None of them.
47.______ is an example for programmable interrupt controller.
a)8259A b)8285 c)8080 d)8585
48. the command word OCW1 is used for ____ interrupt requests.
a)masking b)unmasking C)interrupt d)No interrupt
50.the LOCK pin indicates that an instruction with a ____ prefix is being executed and the bus is not to be used by another potential master
a)Unlock b)lock c)wait d)no wait
51. ______ is an example for programmable interrupt controller
a) 8259A b)8080 c)8585 d)2825
52. MULTIBUS is designed to support _____ device and can be used
a)8 bit b)16 bit c)both a & b d)None of these
53. the MULTIBUS has ____ address lines.
a)16 b)20 c)12 d)8
54. the 8259A assumes that an acknowledgment consists of ___ pulses, thus making it compatible with 8086 system.
a)one positive b)two negative c) two positive d) one negative
55. The _____ words are used to dynamically control the processing of interrupt.
a)operation command b) multiply command c) divide command d)None of these
56. wait states are inserted between _____ when a memory or I/O interface is not able to respond quickly enough during a transfer
a)T3 b)T4 c)both a & b d)None of these
57. if an input is being conducted ,RD is activated low during T2 and AD15 -AD0 enter a ______ state in preparation for input
a) High impedance b)Low impedance c)Both a& b d)None of them
58. The ______ pins are to allow the system external to the processor to interrogate the status of the processor instruction queue so that it can determine which instruction it is currently executing
a)QS0 b)QS1 c) both a & b d)None of them
59. the meaning of the MCE/PDEN output depends on the mode, which 9s determined by the signal applied to____
a)IOB b)BOB c)COB d)None of them
60. the _____ mode is used for a small system with a single processor
a)maximum mode b)minimum mode c)both d)None
Q.61. convert the decimal number 123.45 to octal
a)173,3 b)172.33 c)122.33 d)123.33
Q 62. convert the hexadecimal number ABC to binary
a)101010111101 b) 1010101111 c) 10101011 d) 10101
Q 63. convert the hexadecimal number ABC to octal
a)5275 b)5024 c)5050 d)5020
Q.64. convert the decimal number 123.45 to hexadecimal
a)FB.3 b)FB.4 c)FA.3 d)None
Q.65. the octal number 1247 in hexadecimal system is____
a)2A7 b)2A6 c)A27 d)none
Q 66. if the segment in different object modules have the same name and the combine type is COMMON , then they are overlaid so that they have the___
a) Different Beginning Address b)Same Beginning Address
c)Same End Address d)Different END Address
Q.67. Stack facilities normally involve the use of indirect addressing through a special register called_
A)AP b)SP c)AC d)PC
Q.68. After the interrupt has been executed the return is made to the interrupted program by an instruction that pops the _ from the stack.
a) IP, CS and PSW b)IP Only c)CS only d)None of these
Q .69.if a procedure is given a FAR attribute , then all calls to it must be ___ calls even if the call is from the same code segment.
a) intransigent b)intersegment c) Both a & b d)None of these
Q.70. A __ is a segment of code that needs to be written only once but whose basic structure can be caused to be repeated several times within a source module by placing a single at the point of each appearance
a)macro b)program c)None of these d)both a & b
Q.71. when a macro call is encounter by the assembler , the assembler replace the call with the macro's code .this replacement action is referred to as__
a)a macro expansion b) a micro expansion c) mini expansion d)None of these
Q.72.For a program to be executed by emulation ,the ____instruction, which is an alternate mnemonic for the WAIT instruction. must be used for synchronization.
a)WAIT b)BWAIT c)FWAIT d)None of these
Q.73. A primary reason for using the tempory real format for internal data storage is to reduce the chances for ________ during a series of calculations which produce a final result that 9s within the required range.
a) overflow b)underflow c)both a and b d) None of these
Q.74.the long real format has ____ exponent bits and _ fraction bits
a)11 b)52 c) both a & b d)None of these
Q.75. the WAIT instruction preceding the ESC instruction causes the 8086 to enter a wait state until its pin___ become active.
a)TEST b)WAIT c)FOR d)LOOP
1. Two's complement representation of -2 is__
a) 110 b)0110 c)1110 d)none of these
2. the binary representation of decimal number 0.375 is___
a) 1110 b)01110 c)0.011 d)1.001
3.8085 model includes ___-register
a) one b)two c)six d)seven
4.8085 has ____ general purpose register to store ___ bit data
a) one ,3 b)two ,4 c) six,8 d)none of these
5. this 16 bit register deals with sequencing the execution of instructions_
a)ac b)dc c)pc d)none of these
6. the beginning of the stack is defined by loading 16 bit address in the ____
a)pc b)ac c)sp d)none of these
7.the size of 8085 address bus is ____ bit
a) two b)three c )16 d)8
8.state TRUE/False ; trap is an un makeable interrupt.
a) FALSE b) TRUE c)NO comment d)Both a & b
9. these two pins provide connection for an external frequency_____
a)A,B b) A,C c)x1,x2 d)none of these
10_________ flag is set to 1 by the instruction just ending if the A register contains a result of all 0's
a)Non Zero b)Carry c)Zero d)None of thes
11 Ac flag is set to a 1 by the instruction just ending if a carry occurred from bit _ to bit___ of the A register during the instruction's execution
a) 1,2 b) 2,3 c)3,4 d)2,3
12.in the case of ____ addressing mode , the instruction directly specifies the absolute location of the data
a)indirect b) xdirect c)direct d)none of these
13.in a three byte instruction , the first byte specifies the opcode , and the following two bytes specify the______
a) 8-bit b) 2 bit c)16 bit d)none of these
14.the LDA instruction moves a byte from memory in to _____ register
a) B register b) c register c)A register d)none of these
15. the CMC and STC instruction allow direct control of the ____ flag by the programmer.
a) Zero flag b) AC flag c) carry flag d)none of these
16. when the OPUSH PSW is encountered the contents of the _ is pushed onto the stack first ,followed by the ____
a)A register ,Byte b) A register, B flag c)A register, flag byte d)none of these
17. the function of the program counter is to point to the memory address from which ____ is to be fetched.
a)first byte b) prv. byte c)next byte d)none of these
18. The___ instruction causes the contents of H&L register to be exchanged with the two bytes which are currently on the top of the system stack.
a)XTPL b)XTML c)XTHL d)HTML
19. ___ flag of the 8086 is set if there is a carry out of bit 3 during an addition operation
a) carry flag b)Zero flag c) Auxiliary carry flag d)none of these
20. ____ register is used an implied counter by creation instructions
a)AX b) Bx c) Cx d)none of these
21state TRUE?FALSE if the DF is cleared ,the string is processed from the higher address towards the lower address
a)TRUE b) FALSE c)no comment d)None of these
22. the size of effective address of 8086 is ___ bits
a) 8 b)12 c)16 d) 32
23.State TRUE/FALSE instruction register of 8086 is LIFO queue
a)TRUE b) FALSE c)no comment d)None of these
24. the next instruction being executed is pointed by_ register
a) Ac b) BC c)PC d)none of these
25.the addressing mode in which the effective address of the datum is in the BX or an index register is_____
a)direct b)register direct c)indirect d)none of these
26. state TRUE?FALSE if a displacement or immediate operand is 2 bytes long, the lower order byte always first
a)TRUE b) FALSE c)no comment d)None of these
27. which field of an instruction indicates what the computer is to do
a) operand b) instruction c) opcode d)none of these
28. the execution time of an instruction can be determined by multiplying the number of clock cycles needed to execute the instruction by the _____
a) cycle b)alarm c)Clock period d)None of these
29. state TRUE/FALSE for a given two operand instruction a register to memory operation is slower than a memory to register operation.
a)TRUE b) FALSE c)no comment d)None of these
30.___ the size of 8086 instruction
a) 1 byte b) 2 bye c) 1 to 6 byte d) 1to 32 byte
31 A _ is an identifier that is assigned the address of the first byte of the instruction in which it appears
a)label b)statement c) goto d)none of these
32. if there are two operands the ____ operand appears first
a) source b)destination c)Both d)none of these
33.state TRUE/FALSE LEA instruction does not affect flags.
a)TRUE b) FALSE c)no comment d)None of these
34.state TRUE/FALSE Neither operand in the XCHG instruction can be immediate
a)TRUE b) FALSE c)no comment d)None of these
35.the CBW and CWD instruction, are designed to aid the ______ process.
a) plus b) minus c) sign extension d)none of these
36. The INC,DEC and NEG instruction have ___ operands
a) one b)Two c)three d)Four
37. The ____ flag is needed to indicate the carry out of bit 3,the MSB of the low order nibble
a)CF b)DF c)AF d)DF
38.in conditional branch instructions ,the distance between the address of the next instruction and branch address to the range _____ byte
a)0 to 127 b) 125 to 255 c) 128 to 127 d)None of these
39. All conditional branch instruction have the ____ byte machine code format.
a) one b)Two c)three d)Four
40.A___ instruction causes the computer to cease its operations.
a) DLT b)CLT c)HLT d)ADS
41.The instruction used to clear interrupt flag in 8086 is_______
a)CLI b) HLT c)CWX d)None of these
42. ______ instruction does not automatically insert zeroes from the left, instead extends the sign of the operand by repeatedly inserting the MSb
a)SAR b)BAR c)CAR d)DAR
43. The instruction used to rotate left through carry is________
a)ACL b)BCL c)RCL d)None of these
44.the directive used to define a Double Word is______
a)DD b)BB c)CC d)None of these
45. The directives and instruction that appear between the _______ directives are considered to be contained in the segment.
a) segment b)Record c)ENDS d)Both a and c
46,. The output of an assembler is______-
a) Object Module b)Listing c)Both a and b) d)None of them.
47.______ is an example for programmable interrupt controller.
a)8259A b)8285 c)8080 d)8585
48. the command word OCW1 is used for ____ interrupt requests.
a)masking b)unmasking C)interrupt d)No interrupt
50.the LOCK pin indicates that an instruction with a ____ prefix is being executed and the bus is not to be used by another potential master
a)Unlock b)lock c)wait d)no wait
51. ______ is an example for programmable interrupt controller
a) 8259A b)8080 c)8585 d)2825
52. MULTIBUS is designed to support _____ device and can be used
a)8 bit b)16 bit c)both a & b d)None of these
53. the MULTIBUS has ____ address lines.
a)16 b)20 c)12 d)8
54. the 8259A assumes that an acknowledgment consists of ___ pulses, thus making it compatible with 8086 system.
a)one positive b)two negative c) two positive d) one negative
55. The _____ words are used to dynamically control the processing of interrupt.
a)operation command b) multiply command c) divide command d)None of these
56. wait states are inserted between _____ when a memory or I/O interface is not able to respond quickly enough during a transfer
a)T3 b)T4 c)both a & b d)None of these
57. if an input is being conducted ,RD is activated low during T2 and AD15 -AD0 enter a ______ state in preparation for input
a) High impedance b)Low impedance c)Both a& b d)None of them
58. The ______ pins are to allow the system external to the processor to interrogate the status of the processor instruction queue so that it can determine which instruction it is currently executing
a)QS0 b)QS1 c) both a & b d)None of them
59. the meaning of the MCE/PDEN output depends on the mode, which 9s determined by the signal applied to____
a)IOB b)BOB c)COB d)None of them
60. the _____ mode is used for a small system with a single processor
a)maximum mode b)minimum mode c)both d)None
Q.61. convert the decimal number 123.45 to octal
a)173,3 b)172.33 c)122.33 d)123.33
Q 62. convert the hexadecimal number ABC to binary
a)101010111101 b) 1010101111 c) 10101011 d) 10101
Q 63. convert the hexadecimal number ABC to octal
a)5275 b)5024 c)5050 d)5020
Q.64. convert the decimal number 123.45 to hexadecimal
a)FB.3 b)FB.4 c)FA.3 d)None
Q.65. the octal number 1247 in hexadecimal system is____
a)2A7 b)2A6 c)A27 d)none
Q 66. if the segment in different object modules have the same name and the combine type is COMMON , then they are overlaid so that they have the___
a) Different Beginning Address b)Same Beginning Address
c)Same End Address d)Different END Address
Q.67. Stack facilities normally involve the use of indirect addressing through a special register called_
A)AP b)SP c)AC d)PC
Q.68. After the interrupt has been executed the return is made to the interrupted program by an instruction that pops the _ from the stack.
a) IP, CS and PSW b)IP Only c)CS only d)None of these
Q .69.if a procedure is given a FAR attribute , then all calls to it must be ___ calls even if the call is from the same code segment.
a) intransigent b)intersegment c) Both a & b d)None of these
Q.70. A __ is a segment of code that needs to be written only once but whose basic structure can be caused to be repeated several times within a source module by placing a single at the point of each appearance
a)macro b)program c)None of these d)both a & b
Q.71. when a macro call is encounter by the assembler , the assembler replace the call with the macro's code .this replacement action is referred to as__
a)a macro expansion b) a micro expansion c) mini expansion d)None of these
Q.72.For a program to be executed by emulation ,the ____instruction, which is an alternate mnemonic for the WAIT instruction. must be used for synchronization.
a)WAIT b)BWAIT c)FWAIT d)None of these
Q.73. A primary reason for using the tempory real format for internal data storage is to reduce the chances for ________ during a series of calculations which produce a final result that 9s within the required range.
a) overflow b)underflow c)both a and b d) None of these
Q.74.the long real format has ____ exponent bits and _ fraction bits
a)11 b)52 c) both a & b d)None of these
Q.75. the WAIT instruction preceding the ESC instruction causes the 8086 to enter a wait state until its pin___ become active.
a)TEST b)WAIT c)FOR d)LOOP
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