BCA-2 & MCA-1 Computer Organization and Arch.

PART-A

1. The term __________ relates to the art of putting together components to arrive at a system that performs well according to a set of goals.
(A) Computer architecture (B) Computer organization
(C) Both (D) None
2. ________ and __________ together called as a processor or CPU.
(A) Memory, ALU (B) ALU, CU (C) CU, Memory (D) None
3. The time required to access one word is called ____
(A) Cycle time (B) Access time (C) Transfer time (D) None
4. The number of bits in each word is called _____
(A) Data length (B) Bit length (C) Word length (D) Char length
5. _____ memory stores system programs, large data files and the info which is not regulate used by the CPU.
(A) Primary memory (B) Secondary memory (C) Cache (D) Internal memory
6. The system performance can be improved by placing a small fast acting buffer memory between the processor & main memory called ______
(A) Internal (B) Primary (C) Secondary (D) Cache
7. In which memory we have to follow the location access, waiting, fetching process.
(A) Sequential (B) Direct (C) Random (D) Associative
8. The purpose of ____ is to control the system operations by routing the selected data items to the selected processing data at the right time.
(A) ALU (B) CU (C) CPU (D) None
9. Control unit has responsibilities ___________
(A) Instruction interpretation (B) Instruction sequencing
(C) Both (D) None
10. In ______ control unit determines the address of the next instruction to be execute.
(A) Instruction interpretation (B) Instruction sequencing
(C) Both (D) None
11. According to john von Neumann, for a machine to be a computer it must have the
(A) Addressable memory (B) ALU
(C) Program counter (D) All above
12. ______ is a register which holds the memory address of the next instruction.
(A) PC (B) IR (C) ACC (D) None
13. ______ is a register holds correct instruction being executed.
(A) PC (B) IR (C) ACC (D) None
14. _____ is a register designated to hold the result of an operation performed by the ALU.
(A) PC (B) IR (C) ACC (D) None
15. Which is a computer architecture
(A) Stack machine (B) Accumulator machine (C) Both (D) None
16. A collection of lines that connects several devices is called.
(A) Wire (B) Path (C) Bus (D) None
17. In ____ bus structure I/O units are connected to the processor through an I/O bus & the processor is connected to memory through memory bus
(A) Single (B) Two (C) Three (D) None
18. Operations codes in short op codes are represented using ______.
(A) English word (B) Mnemonics (C) ASCII Code (D) None
19. ASCII – encoded characters are usually stored and transferred as ____ per character.
(A) 8 Bit (B) 8 Byte (C) 16 Bit (D) 16 Byte
20. ______ is referred to as ASCII in the USA.
(A) IRA (B) IANA (C) IAER (D) None
21. ________ character set is used in IBM 370 machines It is an 8 – bite code.
(A) ASCII (B) IRA (C) EBCDIC (D) None
22. Vax is a ______ oriented machine.
(A) Bit (B) Byte (C) Word length (D) None
23. In signed integers, if the MSB is I the number is considered as __________.
(A) Positive (B) Negative (C) Character (D) None
24. Operations for manipulating individual bits of a word are ____ instructions.
(A) Jump (B) Skip (C) Bit twiddling (D) Return
25. Notation for contents of an address field in the instruction.
(A) A (B) R (C) EA (D) X
26. Algorithm for register indirect addressing is
(A) EA = A (B) EA = R (C) EA = (R) (D) EA = A + (R)
27. In ___________ addressing mode instruction, operand is actually present in the instruction.
(A) Direct (B) Indirect (C) Immediate (D) None
28. In _____ addressing mode, operand is held in register named in address field.
(A) Direct (B) Immediate (C) Register (D) None
29. ADD A is an example of _____ addressing
(A) Indirect (B) Immediate (C) Register (D) None
30. When a program branches to a subroutine we say that it is _______.
(A) Calling the subroutine (B) Subroutine linkage
(C) Parameter passing (D) None
31. The _____ is responsible for moving data to memory or I/O module.
(A) CU (B) ALU (C) CPU (D) None
32. Using finite precision ten’s complement, if both numbers for addition are positive and results negative then the circuit reports ___________
(A) Under flow (B) Overflow (C) Normal (D) Not certain
33. Overflow can occur only when adding two numbers that have the ________ sign.
(A) Same (B) Different
34. Magnetic memory is
(A) RAM (B) CD (C) Hard disk (D) All
35. ______ consist of the access time plus any additional time required before a second access can commence.
(A) transfer time (B) Cycle time (C) Associative time (D) None
36. _____ memory consists of peripheral storage devices like hard disks magnetic tapes, etc.
(A) CPU (B) Internal (C) external (D) None
37. _______ memory require periodic refreshing
(A) Dynamic RAM (B) ROM (C) Static RAM (D) None
38. In ZD memory organization no. of address lines equals to _______.
(A) ZW (B) Log 10 w (C) Log 2 w (D) None
39. Bipolar transfer and ______ transistor are used for deciphering RAM
(A) MOS (B) NOS (C) COS (D) None
40. A bulk of a modern processor memory is composed of _______.
(A) DRAM (B) SRAM (C) PROM (D) None
41. 1671 the german mathematician and philosopher _______ constructed a calculator that could perform multiplication and division.
(A) Charles Babbage (B) Gottfried Leibniz (C) Herman Hollerith (D) None
42. Analytical engine was designed to be a general purpose device that is capable of performing any mathematical operation _______.
(A) Automatically (B) Manually (C) both A & B (D) None
43. ______ provides means for communication among the control unit, ALU and register of the CPU.
(A) Control Bus (B) System Bus (C) CPU interconnection (D) None
44. The number of bits in each word is called as _____ of the computer.
(A) Word (B) Word length (C) Date length (D) CM Chick
45. The time required to access one word is called ______.
(A) Cycle time (B) Memory access time (C) Transfer time (D) None
46. ______ are least partially visible register type also referred to as flags.
(A) Index register (B) Stock pointer (C) Condition codes (D) None
47. The CPU read instruction from the memory called
(A) Fetch instruction (B) Fetch data (C) Interpret instruction (D) None
48. In ______ machine, operands of the ALU are always the top two registers of the set and the result from the ALU is stored in the top register of the set.
(A) Stack (B) Accumulator (C) Load/store (D) None
49. _______ perform the operation indicated in the instruction.
(A) Do (B) OS (C) Of (D) None
50. CPU always _______ the PC after each instruction fetch.
(A) Increments (B) Decrements (C) Branch (D) None
51. _____________are used for business data processing when computing and storage is capacity is larger than the minicomputers can handle
(A) Micro computer (B) Minicomputer (C) Mainframe computer (D) Super computer
52. __________refers to those attributes of computer system which are visible to a programmer
(A) Stricture (B) Architecture (C) Organization (D) None of these
53. Structure of Babbage difference engine consisted of __________registers
(A) Electrical (B) Electronics (C) Mechanical (D) All of these
54. ________defines the way in which the components of a computer are interrelated
(A) function (B) Structure (C) Organization (D) Architecture
55. __________defines the operation of each individual component as a part of the structure
(A) Function (B) Organization (C) Structure (D) Architecture
56. ___________refers to the operational units of a computer
(A) Function (B) Organization (C) Architecture (D) None of these
57. Program is ___________
(A) List of instruction (B) Internal storage (C) Collection of interrelated data (D) None of these
58. Charles Babbage designed machine
(A) Difference engines (B) Analytical engine (C) Both A & B (D) None of these
59. Component of “Analytical engine” the mill corresponds to a modern
(A) Control unit (B) Memory (C) ALU (D) CPU
60. Which type of computer are small devices that are often used to control other devices
(A) Mini computer (B) Main frame computer (C) Embedded computer (D) N one of these
61. A___________is an entity that interest in some or the other way with its external environment
(A) Computer (B) CPU (C) Buses (D) All

62. CPU is ___________
(A) Central processing unit (B) Command processing unit (C) Control processing unit (D) None of these
63. Bus can also be a wire or a communication line or in general it can be referred to as a ______
(A) System interconnection (B) Data bus (C) Address bus (D) Control bus
64. ___________is used store the instructions data and the result as well
(A) Memory (B) ALU (C) Buses (D) CPU
65. __________Perform the calculations on the input data
(A) ALU (B) Memory (C) CU (D) CPU
66. ___________are used to more data from the computer and its external environment
(A) Input output interface (B) CPU (C) Memory (D) All of these
67. Input output technique______
(A) Programmed (B) Interrupt drive (C) Direct memory access (D) All of these
68. ______is the first digital computer in which the VON NEUMANN architecture are employed
(A) JAS (B) EDVAC (C) ENIAC (D) None
69. input and output equipment operated by the
(A) ALU (B) Memory (C) Control unit (D) None
70. Magnetic hard disk is example of
(A) Internal memory (B) Primary memory (C) Secondary memory (D) Cache memory
71. The register in the CPU serve function.
(A) User visible register (B) control and status registers
(C) Both a & b (D) none of these.
72. The bit of flag register are set according to the
(A) result of operation (B) input data condition (C) memory address ( D) all of above
73. ___________________ enable the anarchize or assemble language programmer to minimize main memory reference by use of register.
(A) cache memory (B) use visible register (C) virtual memory (D) none of these
74. CPU register are.
(A) Instruction register (B) user visible (C) memory buffer register (D) All of these
75. index register : these are for indexed addressing and may be
(A) auto indexed (B) direct indexed (C) both a & b (D) none
76. the most popular computer architectures are:
(A) Stack machine (B) accumulation machine (C) load/store machine (D) fill of these
77. flag of 8085 are-
(A) Memory register (B) stake pointer
(C) Condition codes (D) program counter
78. ___________ number of flag bits are defined in 8085
(A) Five (B) four (C) six (D) seven
79. Z8000 consists of _____________ 16 bit general purpose register.
(A) seven (B) eight (C) sixteen (D) nine
80. zilog z8000 uses ______________ register to hold a single address.
(A) Two (B) six (C) four (D) five

PART-B

1. Four registers are essential to instruction execution
(1) Program counter (2) Instruction register
(3) Memory address register (4) Memory buffer register
(A) 1, 2 (B) 2, 3 (C) 3, 4 (D) All
2. the three most popular computer architecture are
(1) The stack machine (2) The accumulator machine
(3) The load/store machine (4) The register machine
(A) 1, 2 (B) 2, 3 (C) 1, 2, 3 (D) All
3. In addiction to the wires that carry the data, the computer must have some lines for ______ purpose.
(1) Data transferring (2) Addressing (3) Controlling
(A) 1, 2 (B) 2, 3 (C) 3, 1 (D) All
4. Control lines are
(1) Memory write (2) reset (3) Bus grant (4) Transfer ACK
(A) 1, 2 (B) 2, 3 (C) None (D) All
5. Instructions fall into four categories are
(1) Data processing (2) Address storage (3) Address movement (4) Address control
(A) 1 (B) 1, 2 (C) 2, 3 (D) All
6. The most important general categories of data are
(1) Addresses (2) Numbers (3) Characters (4) Logical data
(A) 1, 3 (B) 2, 4 (C) None (D) All
7. VAX data types are
(1) Binary integer (2) Floating point (3) Decimal (4) Character
(A) 1, 2 (B) 2, 3 (C) 3, 4 (D) All
8. data transfer instructions are
(1) Move (2) Store (3) Load (4) Exchange
(A) 1, 2, 3 (B) 2, 3, 4 (C) 3, 4, 1 (D) All
9. Addressing modes are ____________
(1) Immediate addressing (2) Direct addressing
(3) Indirect addressing (4) Register addressing
(A) 1, 2, 3 (B) 2, 3, 4 (C) 3, 4, 1 (D) All
10. _________ are the example of data structures
(1) List (2) Linked list (3) Arrays (4) Graphs
(A) 1, 2 (B) 3, 4 (C) 2, 4 (D) All
11. The call instruction is just a special branch instruction that performs
(1) Store the contents of the DC in link register
(2) Branch to the target address specified by the instruction.
(A) 1 (B) 2 (C) 1, 2 (D) None
12. There are memory systems :-
(1) Internal (2) External (3) SRAM (4) DRAM
(A) 1, 2 (B) 2, 3 (C) 3, 4 (D) All
13. Unit of transfer for internal memory is equal to the number of data lines into and out of memory module based upon.
(1) Bit (2) Byte (3) Word (4) Block
(A) 1, 2 (B) 2, 4 (C) 3, 4 (D) All
14. Memory access methods are
(1) Sequential (2) Direct (3) Random (4) Associative
(A) 1, 2 (B) 2, 3 (C) 3, 4 (D) All
15. Physically memory are
(1) Semiconductor (2) Magnetic (3) Optical (4) Magnate optical
(A) 1, 2 (B) 2, 3 (C) 1, 4 (D) All
16. Types of random access memories are
(1) ROM (2) PROM (3) EPROM (4) EEPROM
(A) 1, 2 (B) 1, 3 (C) 1, 3, 4 (D) All
17. Three state of self in ROM
(1) Control (2) Select (3) Data read (D) Data write
(A) 1, 2, 3 (B) 2, 3, 4 (C) 1, 3, 4 (D) All
18. Data transfer between the main memory and CPU register takes place through two register’s are
(1) MAR (2) MBR (3) MCR (4) MDR
(A) 1, 2 (B) 2, 3 (C) 3, 4 (D) 1, 4
19. The technology used for deciphering RAM’S are
(1) SRAM (2) DRAM (3) Bipolar transistor (4) MOS transistor
20. Which of the given statement is true for static RAM?
(1) Bipolar Memories (2) Higher density
(3) Battery powered system (4) Refresh circuitry
(A) 1, 2 (B) 1, 3 (C) 2, 3 (D) 2, 4
21. The list of instruction is called _______ and internal storage is called_____.
(M) Program (N) Language (X) Memory (Y) Database
(A) MX (B) MY (C) NX (D) NY
22. ____ defines the way in which the components of a computer are interrelated. ________ define the operation of each individual component as a part of the structure.
(M) Structure (N) Function (O) Architecture
(A) MN (B) NM (C) MO (D) NO
23. _______ contains the address of an instruction to be fetched and _______ contains the instruction most recently fetched.
(M) Program counter (N) Instruction register (O) Memory buffer register
(A) MN (B) NM (C) MO (D) NO
24. In the accumulator machine ordering of instruction should be
(M) Store the contents of the accumulator back into the memory
(N) Execute the add instruction.
(O) Place one of the numbers into the accumulator
(A) MNO (B) NOM (C) OMN (D) ONM
25. Zilog Z800 user ______ registers to hold a single address Intel 8086 has ______ 16-bit segment number and a bit offset.
(M) 2 (N) 4
(A) MN (B) NM (C) MM (D) NN
26. The occurrence of one event on a bus follows and depends on the occurrence of a previous event is ______ bus timing and ______ bus has specific function.
(M) Synchronous (N) Asynchronous (O) Functional dedication (P) Multiplexed.
(A) MO (B) NO (C) MP (D) NP
27. DMA is also called _____ & 1984; IBM was shipping its _______ model.
(M) PPU (N) CU (O) PCAT (P) ISA
(A) MO (B) MP (C) NO (D) NP
28. _____ indicates that data has been accepted from or placed on the bus and _____ acknowledges that the pending interrupt has been recognized.
(M) Transfer ACK (N) Interrupt ACK (O) Bus request
(A) MN (B) NM (C) MO (D) NO
29. (M) Transfer ACK (N) Interrupt ACK (O) Bus request
(A) MN (B) NM (C) MO (D) NO
30. _____ used to synchronize operations ________ incliner all modules
(M) Clock (N) Reset
(A) MN (B) NM (C) MM (D) NN
31. Intel 8086 has _________ 16 bit pointer and index register.
(A) Five (B) four (C) six (D) two
32. the processing required for a single instruction is called an ________
(A) Program counter (B) instruction (C) both a & b (D) None of these
33. CPU always _________ the PC after each instruction fetch.
(A) Increment (B) decrement (C) not change (D) fetch instruction
34. the fetch instruction us stored in a register in the CPU known as
(A) Program counter (B) general purpose
(C) Stack register (D) instruction register
35. During the instructor cycle instruction address calculation, instruction fetch and instruction operation decoding are performed.
(A) Only once (B) multiple times (C) two times (D) none of these
36. A stack machine implements a stock with -
(A) Accumulator (B) CPU (C) pointer (D) register
37. A accumulator machine has a special register, called an
(A) Stack pointer (B) program counter (C) accumulator (D) none of these
118. The CPU of 8085 is organized around a single _____________ internal.
(A) 8 bit (B) 16 bit (C) 20 bit (D) None
38. _____________Communicate with main memory through address bus & Data Bus.
(m) MAR (B) MBR (C) Both (C) none
39. __________ are used for storing the data generated by one instruction for later used by other instruction.
(a) Accumulators (b) GPRs (c) SPRs (D) Temporary Registers
40. State True /False
(1) ALU carry out the instruction form I/O devices to processor
(2) ALU perform storing computation and accessing data
(3) ALU perform the calculations on the input data
(A) TTT (B) FFF (C) FTF (D) FFT

PART-C
1. True or false :-
(1) The data transfer rate of peripherals is often much slower than that of the memory or CPU.
(2) External devices broadly can be classified into two categories human readable & machine readable
(3) The transducer converts the data from electrical signal and recovers
(4) The I/O module must be able to perform device communication.
(A) FFTT (B) TTFF (C) FFFF (D) TTTT
2. True or false :-
(1) The transfer rate into and out of main memory or CPU is very low and the rate is quite higher for most at the peripheral.
(2) I/O module a never responsible for error defection and subsequently reporting errors to the CPU.
(3) Mechanical and electrical malfunctions types of error are reported by the device such as paper jam, hard disk track etc.
(4) A program monitor SIN and when SIN is set, the processor real the contents of DATA IN
(A) TTFF (B) FFTT (C) TTTT (D) FFFF
3. True or false :-
(1) An I/o module that take most of detailed processing burden, presenting to a high level CPU, is usually referred to as I/O controller.
(2) An I/O module that is primitive and requires detailed control is usually referred to as an I/o channel
(3) Three techniques are possible for I/O operation informed I/o, interrupt driven, DMA
(4) In interrupt driven I/O the CPU is responsible for extracting date from main memory for output and storing data in main memory for input.
(A) TTFF (B) FFTT (C) TTTF (D) TTTT
4. The sequence of action that takes place with programmed I/o are.
(1) CPO requests I/O operation
(2) I/O module performs operation
(3) I/O module sets status bit
(4) CPU checks status bit periodically
(A) 1, 2, 3, 4 (B) 2, 3, 4, 1 (C) 3, 4, 1, 2 (D) 4, 3, 1, 2
5. True or false :-
(1) Four types of I/O commands can be received by the I/o module when it is addressed by CPU.
(2) A control command is used to test various status condition associated with an I/o module and its peripherals
(3) A test command is used to activate a peripheral and tell what to do
(4) CPU commands contain identifier (addressing I/O device)
(A) TFFT (B) FTTF (C) TTTF (D) TTTF
6. True or false :-
(1) The branch operation is usually implemented by one machine instruction.
(2) Due to wasting of type interrupt driven I/o is replaced by program controlled I/o.
(3) An interrupt is indicated by a signal sent by the device interface to the CPU via an interrupt request line.
(4) The CPU runs a program called an interrupt handler.
(A) FFTT (B) TTFF (C) TTTF (D) TTTT
7. True or false :-
(1) Priorities may be used to control the nesting of interrupts
(2) The interrupt service routine saves all registers so that they can be restored later.
(3) The DMA module is capable of mimicking the CPU.
(4) When the CPU wishes to read or write a block of data, it issues a command to the DMA module.
(A) TTTT (B) FTFT (C) TFTF (D) FFFF
8. True or false :-
(1) Fly by DMA transfer is the fastest DMA transfer type and is also referred to as a single cycle, single address.
(2) A DMA controller has one or more status registers that are read by the CPU to determine the state of each DMA channel.
(3) Channels must be enabled by the processor for the DMA controller to respond to DMA requests.
(4) In has master mode, the DMA controller acquires the system has from the CPU to perform the DMA transfers.
(A) TTTT (B) FFFF (C) TTFF (D) FFTT
9. True or false :-
(1) There are three DMA transfers
(2) Fetch deposit DMA transfer is the fastest DMA transfer type.
(3) Keeping the interrupts for a long time will increase the interrupt latency.
(4) A single instruction that performs test as well as control could be used to perform an atomic transaction.
(A) TTTT (B) TTFF (C) FFTT (D) FFFF
10. True or false :-
(1) Internal data paths are used to move data between the registers and ALU.
(2) The control unit uses clock to maintain the timing
(3) Flags are heeded by the control unit to determine the status of CPU.
(4) The control unit uses clock to maintain the timing
(A) FFFF (B) TTTT (C) TFTF (D) FTFT
11. True or false :-
(1) MAR & MDR communicate with main memory through address bus and data bus.
(2) temporary registers are always used for storing the data generated by one instruction for later used by another instruction.
(3) In asynchronous transfer one of the control lines of the bus carries clock pulses which provide timing signals to the CPU and the main memory.
(4) The ALU Performs arithmetic and logic operations.
(A) TFFT (B) FTTF (C) FFTT (D) TTFF
12. True or false :-
(1) ALU has no internal storage.
(2) Contents of PC are loaded into MAR is the first step of instruction execution.
(3) The required control signals are determined based on the content at control counter, IR and flags.
(A) TTTT (B) FTFT (C) TFTF (D) FFFF
13. True or false :-
(1) Michael Flynn introduced a classification of various computer architectures based on notions at instruction and data streams.
(2) Look ahead techniques were introduced to pre – fetch instructions.
(3) Functional parallelism was supported buy two approaches.
(4) Vector computers are equipped with scalar and vector hardware or appears as SIMD
(A) TTTT (B) FFFF (C) TTFF (D) FFTT
14. True or false :-
(1) Implicit or intrinsic parallel computers are those that execute program in MIMD mode.
(2) The major distraction between multiprocessors and multi computers lies in memory shoving.
(3) Inter processor communication is done through message passing among the model.
(4) There are three families at pipelined vector processors.
(A) TFFF (B) TFFF (C) TTTF (D) FTTT
15. True or false :-
(1) The CPU at a modern digital computer can generally be partitioned intro three sections.
(2) To achieve pipelining, one most sub dived the input task into a sequence of sub tasks.
(3) Pipelining is an implementation technique where by multiple instruction are overlapped in execution
(4) The through put of an instruction pipeline is determined by now often an instruction exists the pipeline.
(A) FFFF (B) TFFF (C) TTFF (D) TTTT
16. True or false :-
(1) Pipeline does not reduce the execution time of an individuals instruction.
(2) Pipeline overhead arises from the combination of pipeline register delay and clock skew.
(3) Clock skew also contributes to the lower limit on the clock cycle.
(4) Structured hazards arise from resource confutes.
(A) TTTT (B) FFFF (C) TTFF (D) FFTT
17. (1) The system performance is largely dependent on the organization, storage, capacity and speed of operation of the memory system.
(2) Flags of 8085 are nothing but condition codes
(3) Z 8000 consist of 16-16 bit general purpose register
(4) The processing required for a single instruction is called transfer time.
(A) TTFF (B) FFTT (C) FFFF (D) TTTT
18. Match the following
(1) Internal memory (M) Set of CPU registers
(2) Primary memory (N) Main memory
(3) Secondary memory (O) Stores large data files
(4) Cache memory (P) Buffer memory
(A) 1-M,2-N, 3-O, 4-P (B) 1-N, 2-O, 3-P, 4-M
(C) 1-O, 2-P, 3-M, 4-N (D) None of these
19. (1) The bus that is used to carry the address of the data in the memory and its width is equal to the number of bits in the MBR of the memory.
(2) A single hardware device referred to as bus controller or arbiter is responsible for allocating time on the bus to various components.
(3) A common approach if to include buffer register with the devices to hold the information during transfers.
(4) In single bus system, the three units share a single bus.
(A) FFFF (B) FFTT (C) TTFF (D) TTTT
20. (1) In single bus organization I/O units are connected to the processor through an I/O bus and the processor is connected to the memory through the memory bus.
(2) The PCI Bus was developed by IBM
(3) In most of the modern computers there are only single bus architecture.
(4) Interrupt wait control line Indicates that an interrupt is pending.
(A) TTTF (B) TTFF (C) FFTT (D) FTFT
21. Match the following
(1) P (M) Even parity
(2) CY (N) Overflows
(3) AC (O) Carry between fourth and fifth bit
(4) S (P) Positive/Negative
(A) 1-M,2-N, 3-O, 4-P (B) 1-N, 2-O, 3-P, 4-M
(C) 1-O, 2-P, 3-M, 4-N (D) None of these

22. Match the following
(1) CPU (M) Provide for communication a many CPU, memory & I/P
(2) Memory (N) This is the computation unit
(3) Input/Output interface (O) Store information need by computer
(4) System interconnection (P) Move data from the computer and extern environment
(A) 1-M,2-N,3-O,4-P (B) 1-N, 2-M, 3-P, 4-O
(C) 1-N, 2-O, 3-P, 4-M (D) None of these

23. CPU must carry out the task
(1) Read instruction (2) Store instruction (3) Decode instruction (4) Get operand
(5) Give out/ store the result
(A) 1,2,3,4 (B) 1,2,4,3 (C) 1,3,4,5 (D) All of these
24. Information stored in memory is ________
(1) Data (2) Instruction (3) Garbage
(A) 1 & 2 (B) 2 & 3 (C) 1 & 3 (D) All of these
25. State True /False
(1) Instruction sequencing control unit determine the address of the next instruction to be execute
(2) Control unit perform the calculation on the input data
(3) The time required to access one work is called sequencing time
(A) TFT (B) TTF (C) TTT (D) TFF
26. Match the following
(1) Primary memory (M) Refers to a set of CPU register
(2) Secondary memory (N) CPU directly access the program stored in
(3) Cache memory (O) Magnetic hard disk and CD ROMs
(4) Internal memory (P) This memory placed between processor and main memory
(A) 1-M,2-O,3-P,4-N (B) 1-N, 2-P, 3-M, 4-O
(C) 1-N, 2-O, 3-P, 4-M (D) None

27. Intel 8086 family has different segment and they are referred to as
(1) Code segment (2) memory segment (3) extra segment (4) stake segment
(5) Data segment (6) data segment
(A) 1,2,3,4 (B) 1,3,4,6 (C) 2,3,4,5 (D) 1,4,5,6
28. Match the following
(1) Program counter (M) Contain the instruction must reuntly to memory
(2) Instrument register (N) Contain a word of data to be written to memory
(3) Memory address register (O) Contain address of the instrument to be fetched
(4) Memory buffer register (P) Contain address of location in memory
(A) 1-N,2-M,3-O,4-P (B) 1-M, 2-N, 3-P, 4-O
(C) 1-O, 2-M, 3-P, 4-N (D) None of these

29. State True /False according to program status word -
(1) Zero flag set when result is 0
(2) Carry flag reset when result in carry
(3) Reset if logical compare result is equality
(4) Interrupt flag enable or disable interrupt
(A) TTTF (B) TFFT (C) FFTT (D) FTFT
30. CPU consist of -
(1) Memory (2) register (3) control unit (4) ALU
(A) 1,2,3 (B) 1,3,4 (C) 2,3,4 (D) none